FPGA Logic Circuit Implementation and Synthesis with VHDL Programming: A Learning Approach

Abstract

There are significant numbers of relevant research works available that concerns VHDL programming and Field Programmable Gate Array (FPGA) based hardware design, simulation and implementation. This is because; both the FPGA design and VHDL programming realization are quiet new and useful to accomplish various tasks in the field of research for digital system designed and development of miniaturized embedded system. It is found difficult to understand and put into practice by the learners in the tertiary institution, which still requires rapid training and development. In this paper, we design and demonstrate an FPGA logic circuit using 4-bit BCD adders and parallel 4-bit comparator with a stepwise development of the vital soft logic design flow, simulation and timing analysis. It also presents an educational concept designed for complementing courses offered like FPGA prototype and ASIC design. This perception of FPGA-based design flow will facilitate learner’s understanding, skills and it will provide detailed insights into various aspects of microelectronics, digital logic systems design and VHDL programming.